SAINSMART DDS140 PRO REVIEW HOW TO
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I have been digging aroung in the firmware, trying to find out more about the DDS140 94(0A) command which gives continuously sampled 240Khz data. I can't think of an application where we'd need to know the device time accurately though.

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We won't know exactly when a signal arrived unless we code that information into one of the analog channels. Since this is an RX-only application we don't have to care about latency, so we can let big buffers take care of perceptual continuity. To logically couple the device to the host, I think each host -> device poll should tell the device to keep alive.

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I'm not sure if one can use EP2 and get full bandwidth for iso, but I also don't think it's unreasonable to demand we get an entire USB 2.0 host controller all to ourselves so we don't need to share resources. Meanwhile in the examples I've looked at, EP6 is used for iso and they recommend 512 for iso.

EP2 can be configured to be 4x 1K, and it doesn't look like to me that there are any special considerations to this. Isochronous mode decreases this variance a lot, and for our purposes iso means we require less from the 4K buffer. O0 USB spec says all transfers are initiated from the host, which could result in huge variances to when the host polls the device. This has to be clarified by someone who knows. A totally different approach would be (9.3.4 Auto-In / Auto-Out Modes page 111 ff), with direct streaming. So one FIFO gets filled by the ADC, while the other is being sent to the host. This could be avoided if switching from EP2 EP6 respectively. For the time of data transfer, the scope is 'blind'.

> Data is being sent -> FIFO pointer reaches 0x000. By that, the FIFO size could be increased up to 4k when needed (slower sampling) The question is, will FLAGD be held 'high' only as long as the FIFO is full, or has it to be reseted when it once triggered by 'FIFO Full'? If so, this would mean: ADC is sending data to the FIFO -> FIFO gets full -> FLAGD is triggered (going 'high) -> this raises SLRD, so IFCLK is incrementing the FIFO pointer on each rising edge of IFCLK while SLRD is asserted. FLAGD is then programmed to represent a FIFOFULL state (15.5.3 ff page 223).

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Quote from: doctormord on October 24, 2014, 12:45:03 pm How to implement -> EZ-USB TRM -> 9.2.8 Implementing Synchronous Slave FIFO Reads From 9.3.2., i would guess, they're using EP2 or EP6 with 1024byte size (As the smallest received packets are 1k). So I think your aliasing explanation is right, you have 48/4 You may check if IFCLK is connected to CLKOUT somehow. ) Ganzuul, if I am right that resistor is connected to IFCLK, which when driven by the FX2 can only take on values of 30 and 48Mhz.

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(The original firmware is still in the attached eeprom) Zigrok/Pulseview includes a tool (Zadig) to change the driver for the Cypress on the fly. So firmware-changes could be done at runtime. The Scope enumerates with the standard PID/VID when eeprom jumper is open.

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Actually the firmware is loaded to the Cypress RAM when starting the software (Pulseview). I am guessing you are using Cyconsole to load up the FX2 with the other firmware and then re-enumerating? If we can get that path working it is going to save a lot of development time. This is the 'do nothing' approach! I would rather change the multiplexers to 74HCxxxx. So that is the quality approach Secondly at 5V supply, and 0-1V operating range, linearity is not too terrible and resistance comes in at 400 ohms. (Still unknown, how the negative voltage is generated) In principle, the higher supply voltage should not cause a problem in terms of analogue inputs/outputs, but the multiplexer select lines would need buffering. We don't have higher voltages available here. Running the device at a higher voltage reduces both resistance and non linearity. Putting temperature variability to one side for a minute, I think that this is the key curve for a CD4052 is shown at attachment I note two things.

Doctormord 1) Improving performance of the input stage.

Sainsmart dds140 pro review